1. Field of the Invention
The present invention relates to a display panel for a display device, and more particularly, to a display panel and a method of fabricating the same, which is capable of preventing the damage of a substrate due to static electricity generated on the panel in an array test process.
2. Description of the Prior Art
With the development of information society, various types of requirements for a display device for displaying an image are increasing and, recently, various display devices, such as a Liquid Crystal Display (LCD), a Plasma Display Panel (PDP), and an Organic Light Emitting Diode Display Device (OLED), are being used.
The liquid crystal display among the display devices includes an array substrate including a thin film transistor, an upper substrate having a color filter and/or a black matrix, and a liquid crystal layer interposed between the array substrate and the upper substrate. The liquid crystal display is a device in which an arranged status of the liquid crystal is controlled depending on an electric field applied between two electrodes of a pixel area, thereby adjusting permeability of light to display an image.
Further, the OLED display device includes a thin film transistor, such as a switching transistor and a driving transistor, first and second electrodes, a first substrate including an organic light emitting layer arranged between the first and second electrodes, and a second substrate adhered onto the first substrate. The OLED display device is a device in which the extent of light emitting of the organic material is controlled depending on a magnitude of a voltage or an electric current applied between two electrodes of a pixel area.
FIG. 1 shows an example of a display panel or an array substrate of a related art display device.
A display panel 100 for the liquid crystal display device or the OLED display device has an active area AA for providing an image to a user, and a non-active area NA, which is a peripheral area of the active area AA. The display panel is fabricated by adhering the first substrate, which is the array substrate in which the thin film transistor and the like are formed to define a pixel area, to the second substrate which is an upper substrate in which a black matrix and/or a color filter layer are formed.
In the case of the OLED display panel, the second substrate may only function as a protection substrate.
The array substrate or the first substrate on which the thin film transistor is formed includes a plurality of gate lines GL extending in a first direction, and a plurality of data lines DL extending in a second direction perpendicular to the first direction. Each gate line and each data line define one pixel area P. One or more thin film transistors are formed in one pixel area P, and a gate electrode and a source electrode of each thin film transistor may be connected to a gate line and a data line, respectively.
Further, a gate pad 110 is formed at an end of each gate line GL as a signal pad for applying a gate signal. In FIG. 1, a gate pad (not shown) may be additionally formed at a right side in addition to a gate pad 110 formed at a left side.
Further, a data pad 120 is formed at an upper portion or a lower portion of the display panel 100 as a signal pad for applying a data signal to an end of each data line DL.
On the other hand, an array test process is performed to test whether a defect (for example, a point defect such as a fault of a transistor or a line defect such as a short) in an electrical property of the panel is present after a process of fabricating the array substrate is complete. For the array test, test wirings extend longitudinally in both directions of a display panel in order to simultaneously apply a test signal to all gate pads and/or data pads.
That is, as shown in FIG. 1, a test wiring 140 for data lines simultaneously connecting a plurality of data pads 120 longitudinally extends in the first direction substantially parallel to the gate lines, and a test wiring 130 for gate lines simultaneously connecting a plurality of gate pads 110 longitudinally extends in the second direction substantially parallel to the data lines.
Further, the test wirings 130 and 140 and each pad are connected by connection wirings 150 and 160, which are formed of a metal material identical to that of the pads on an identical layer as that of the pads or on different layers than that of the pads.
When an array test is complete through the test wiring after fabricating the array substrate or the display panel, the display panel is cut along a cutting line 170, thereby completing a process of fabricating the individual display panel.
On the other hand, static electricity may be generated in the process of the array test, and at this time a large voltage or electric current may be momentarily applied. Since the above-mentioned test wirings 150 and 160 are formed longitudinally as a single metal wire, they have a large amount of electric charge. Accordingly, electric charges caused by the static electricity flow into the panel through the test wiring and the connection wiring so as to cause breakdown of internal wirings of the thin film transistor or the panel, thereby causing a defect of the panel.
That is, since the related art test wiring and connection wiring for the array test are formed of a metal pattern identical to the data pad or the gate pad, and have the large amount of electric charge, there is a problem in that static electricity generated in the array test process flows into the panel, thereby causing damage of the panel.